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19-2645; Rev 2 12/06
50, Dual SPST Analog Switches in UCSP
General Description
The MAX4731/MAX4732/MAX4733 low-voltage, dual, single-pole/single-throw (SPST) analog switches operate from a single +2V to +11V supply and handle railto-rail analog signals. These switches exhibit low leakage current (0.1nA) and consume less than 0.5nW (typ) of quiescent power, making them ideal for batterypowered applications. When powered from a +3V supply, these switches feature 50 (max) on-resistance (RON) with 3.5 (max) matching between channels, and 9 (max) flatness over the specified signal range. The MAX4731 has two normally open (NO) switches, the MAX4732 has two normally closed (NC) switches, and the MAX4733 has one NO and one NC switch. The MAX4731/MAX4732/MAX4733 are available in 9-bump chip-scale packages (UCSPTM), along with 8-pin TDFN and 8-pin MAX(R) packages. The tiny UCSP occupies a 1.52mm 1.52mm area and significantly reduces the required PC board area.
Features
o 1.52mm 1.52mm UCSP Package o Guaranteed On-Resistance (RON) 25 (max) at +5V 50 (max) at +3V o On-Resistance Matching 3 (max) at +5V 3.5 (max) at +3V o Guaranteed < 0.1nA Leakage Current at TA = +25C o Single-Supply Operation from +2.0V to +11V o TTL/CMOS-Logic Compatible o -108dB Crosstalk (1MHz) o -72dB Off-Isolation (1MHz) o Low Power Consumption: 0.5nW (typ) o Rail-to-Rail Signal Handling
MAX4731/MAX4732/MAX4733
Ordering Information
PART MAX4731EUA MAX4731ETA MAX4731EBLMAX4732EUA MAX4732ETA MAX4732EBLMAX4733EUA MAX4733ETA MAX4733EBLTEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN/BUMPPACKAGE 8 MAX 8 TDFN-EP** 9 UCSP-9 8 MAX 8 TDFN-EP** 9 UCSP-9 8 MAX 8 TDFN-EP** 9 UCSP-9 TOP MARK -- ALG ABV -- ALH ABT -- ALI ABS
Applications
Battery-Powered Systems Audio/Video-Signal Routing Low-Voltage Data-Acquisition Systems Cell Phones Communications Circuits PDAs
UCSP is a trademark of Maxim Integrated Products, Inc. MAX is a registered trademark of Maxim Integrated Products, Inc.
*Future product--contact factory for availability. **EP = Exposed pad.
Pin Configurations/Functional Diagrams/Truth Tables
TOP VIEW (BUMPS ON BOTTOM)
NO1
IN1 V+
MAX4731
COM1
MAX4731
A3 B3 GND IN2 NO2
GND 4 TDFN 5 NO2 NO1 COM1 IN2 1 2 3 8 7 6 V+ IN1 COM2
TOP VIEW (BUMPS ON BOTTOM)
NC1
IN1 V+
MAX4732
COM1
MAX4732
A3 B3 GND IN2 NC2
GND 4 TDFN 5 NC2 NC1 COM1 IN2 1 2 3 8 7 6 V+ IN1 COM2
A1 B1 C1
A2
A1 B1 C1
A2
C2 COM2 UCSP
C3
C2 COM2 UCSP
C3
MAX4731 IN_ NO_ OFF ON
MAX4732 IN_ 0 1 NC_ ON OFF
Pin Configurations/Functional Diagrams/Truth Tables continued at end of data sheet.
0 1
SWITCHES SHOWN FOR LOGIC "0" INPUT
SWITCHES SHOWN FOR LOGIC "0" INPUT
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
50, Dual SPST Analog Switches in UCSP MAX4731/MAX4732/MAX4733
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) V+ ...........................................................................-0.3V to +12V IN_, COM_, NO_, NC_ (Note 1)....................-0.3V to (V+ + 0.3V) Continuous Current (any pin) ...........................................10mA Peak Current (any pin, pulsed at 1ms, 10% duty cycle) ...20mA Continuous Power Dissipation (TA = +70C) 8-Pin MAX (derate 4.5mW/C above +70C) .............362mW 8-Pin TDFN (derate 24.4mW/C above +70C) .........1951mW 9-Bump UCSP (derate 4.7mW/C above +70C).........379mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Lead Temperature (soldering, 10s) .................................+300C Bump Temperature (soldering, Note 2) Infrared (15s) ...............................................................+220C Vapor Phase (60s) .......................................................+215C
Note 1: Signals on IN_, NO_, NC_, or COM_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating. Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and Convection reflow. Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--Single +3V Supply
(V+ = +3V 10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3V, TA = +25C.) (Notes 3, 4)
PARAMETER ANALOG SWITCH Analog Signal Range VCOM_, VNO_, VNC_ RON V+ = +2.7V, ICOM_ = 5mA; VNO_ or VNC_ = +1.5V V+ = +2.7V, ICOM_ = 5mA; VNO_ or VNC_ = +1.5V V+ = +2.7V, ICOM_ = 5mA; VNO_ or VNC_ = +1V, +1.5V, +2V V+ = +3.6V, VCOM_ = +0.3V, +3V; VNO_ or VNC_ = +3V, +0.3V +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX -0.1 -2 -0.1 -2 -0.2 -4 2.3 0.8 0 19 V+ 50 60 3.5 4.5 9 11 +0.1 +2 +0.1 +2 +0.2 +4 nA nA nA V SYMBOL CONDITIONS TA MIN TYP MAX UNITS
On-Resistance
On-Resistance Matching Between Channels (Notes 5, 6)
RON
On-Resistance Flatness (Note 7)
RFLAT(ON)
NO_ or NC_ Off-Leakage Current (Note 8)
INO_(OFF) INC_(OFF)
COM_ Off-Leakage Current (Note 8)
V+ = +3.6V, ICOM_(OFF) VCOM_ = +0.3V, +3V; VNO_ or VNC_ = +3V, +0.3V V+ = +3.6V, VCOM_ = +0.3V, +3.0V; VNO_ or VNC_ = +0.3V, +3V, or floating
COM_ On-Leakage Current (Note 8)
ICOM_(ON)
2
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50, Dual SPST Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS--Single +3V Supply (continued)
(V+ = +3V 10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3V, TA = +25C.) (Notes 3, 4)
PARAMETER DYNAMIC CHARACTERISTICS Turn-On Time tON VNO_ or VNC_ = +1.5V, RL = 300, CL = 35pF, Figure 2 VNO_ or VNC_ = +1.5V, RL = 300, CL = 35pF, Figure 2 VNO_ or VNC_ = +1.5V, RL = 300, CL = 35pF, Figure 3 VGEN = 0V, RGEN = 0, CL = 1.0nF, Figure 4 Signal = 0dBm, 50 in and out f = 1MHz, VCOM_ = 1VRMS, RL = 50, CL = 5pF, Figure 5 f = 1MHz, VCOM_ = 1VRMS, RL = 50, CL = 5pF, Figure 6 f = 1MHz, Figure 7 +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C +25C +25C 1 7.5 300 -72 40 ns 30 70 150 170 60 70 ns ns SYMBOL CONDITIONS TA MIN TYP MAX UNITS
MAX4731/MAX4732/MAX4733
Turn-Off Time
tOFF
Break-Before-Make (MAX4733 Only, Note 8) Charge Injection On-Channel -3dB Bandwidth Off-Isolation (Note 9)
tBBM
Q BW VISO
pC MHz dB
Crosstalk (Note 10) NO_ or NC_ Off-Capacitance COM_ Off-Capacitance COM_ On-Capacitance LOGIC INPUT Input Logic High Input Logic Low Input Leakage Current SUPPLY Power-Supply Range Positive Supply Current
VCT COFF
+25C +25C +25C +25C 1.4
-108 20 20 40
dB pF pF pF V 0.8 V A V A
CCOM_(OFF) f = 1MHz, Figure 7 CCOM_(ON) f = 1MHz, Figure 7 VIH VIL IIN V+ I+ V+ = +5.5V, VIN_ = 0V or V+, all switches on or off VIN_ = 0V or V+
-1 2.0
+0.005
+1 11
0.0001
1
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3
50, Dual SPST Analog Switches in UCSP MAX4731/MAX4732/MAX4733
ELECTRICAL CHARACTERISTICS--Single +5V Supply
(V+ = +5V 10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5V, TA = +25C.) (Notes 3, 4)
PARAMETER ANALOG SWITCH Analog Signal Range VCOM_, VNO_, VNC_ RON V+ = +4.5V, ICOM_ = 5mA, VNO_ or VNC_ = +3.5V V+ = +4.5V, ICOM_ = 5mA, VNO_ or VNC_ = +3.5V V+ = +4.5V, ICOM_ = 5mA, VNO_ or VNC_ = +1V, +2V, +3V V+ = +5.5V, VCOM_ = +1V, +4.5V; VNO_ or VNC_ = +4.5V, +1V +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX -0.1 -2 -0.1 -2 -0.2 -4 2 0.2 0 8.5 V+ 25 30 3 4 5 7 +0.1 +2 +0.1 +2 +0.2 +4 nA nA nA V SYMBOL CONDITIONS TA MIN TYP MAX UNITS
On-Resistance
On-Resistance Matching Between Channels (Notes 5, 6)
RON
On-Resistance Flatness (Note 7)
RFLAT(ON)
NO_ or NC_ Off-Leakage Current (Note 8)
INO_(OFF) INC_(OFF)
COM_ Off-Leakage Current (Note 8)
V+ = +5.5V, ICOM_(OFF) VCOM_ = +1V, +4.5V; VNO_ or VNC_ = +4.5V, +1V V+ = +5.5V, VCOM_ = +1V, +4.5V; VNO_ or VNC_ = +1V, +4.5V, or floating
COM_ On-Leakage Current (Note 8) DYNAMIC CHARACTERISTICS Turn-On Time
ICOM_(ON)
tON
VNO_ or VNC_ = +3.0V, RL = 300, CL = 35pF, Figure 2 VNO_ or VNC_ = +3.0V, RL = 300, CL = 35pF, Figure 2 VNO_ or VNC_ = +3.0V, RL = 300, CL = 35pF, Figure 3 VGEN = 0V, RGEN = 0, CL = 1.0nF, Figure 4 Signal = 0dBm, 50 in and out f = 1MHz, VCOM_ = 1VRMS, RL = 50, CL = 5pF, Figure 5
+25C TMIN to TMAX +25C TMIN to TMAX +25C TMIN to TMAX +25C +25C 1
47
85 95 ns
23
45 55 ns
Turn-Off Time
tOFF
25 ns
Break-Before-Make (MAX4733 Only, Note 8) Charge Injection On-Channel Bandwidth
tBBM
Q BW
7.5 300
pC MHz
Off-Isolation (Note 9)
VISO
+25C
-72
dB
4
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50, Dual SPST Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS--Single +5V Supply
(V+ = +5V 10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5V, TA = +25C.) (Notes 3, 4)
PARAMETER Crosstalk (Note 10) NO_ or NC_ Off-Capacitance COM_ Off-Capacitance COM_ On-Capacitance LOGIC INPUT Input Logic High Input Logic Low Input Leakage Current SUPPLY Power-Supply Range Positive Supply Current V+ I+ V+ = +5.5V, VIN_ = 0V or V+, all switches on or off 2.0 0.0001 11 1 V A VIH VIL IIN VIN_ = 0V or V+ -1 +0.005 2.0 0.8 +1 V V A SYMBOL VCT COFF CONDITIONS f = 1MHz, VCOM_ = 1VRMS, RL = 50, CL = 5pF, Figure 6 f = 1MHz, Figure 7 TA +25C +25C +25C +25C MIN TYP -108 20 20 40 MAX UNITS dB pF pF pF
MAX4731/MAX4732/MAX4733
CCOM_(OFF) f = 1MHz, Figure 7 CCOM_(ON) f = 1MHz, Figure 7
The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. Note 4: UCSP and TDFN parts are 100% tested at +25C only, and guaranteed by design over temperature. MAX parts are 100% tested at +85C and +25C and guaranteed by design over temperature. Note 5: RON = RON(MAX) - RON(MIN). Note 6: UCSP on-resistance matching between channels and on-resistance flatness guaranteed by design. Note 7: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. Note 8: Guaranteed by design. Note 9: Off-Isolation = 20 log10 (VNO_/VCOM_), VNO_ = output, VCOM_ = input to off switch. Note 10: Between any two switches. Note 3:
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5
50, Dual SPST Analog Switches in UCSP MAX4731/MAX4732/MAX4733
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
ON-RESISTANCE vs. VCOM (V+ = +2.5V)
MAX4731-33 toc01
ON-RESISTANCE vs. VCOM
50 V+ = +2.0V 40 30
ON-RESISTANCE vs. VCOM (V+ = +3.0V)
MAX4731-33 toc02 MAX4731-33 toc03
30 25 20 TA = +85C
25
TA = +85C
RON ()
RON ()
RON () TA = -40C TA = +25C
30 V+ = +3.0V V+ = +5.0V V+ = +10.0V 10
20
15 10 5 0 TA = +25C TA = -40C
20
15
10
0 0 2 4 6 8 10 VCOM (V)
5 0 0.5 1.0 1.5 2.0 2.5 VCOM (V)
0
0.5
1.0
1.5 VCOM (V)
2.0
2.5
3.0
ON-RESISTANCE vs. VCOM (V+ = +5.0V)
MAX4731-33 toc04
ON/OFF-LEAKAGE CURRENT vs. TEMPERATURE
V+ = +5V
MAXZ4731-33 toc05
CHARGE INJECTION vs. VCOM
40 CHARGE INJECTION (pC) 35 30 25 20 15 10 V+ = +3.0V V+ = +5.0V
MAX4731-33 toc06
20
1000 ON/OFF-LEAKAGE CURRENT (pA)
45
16 TA = +85C RON () 12
100 ON-LEAKAGE 10
8 TA = +25C TA = -40C 0 0 1 2 3 4 5 VCOM (V)
4
1 OFF-LEAKAGE 0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
5 0 0 1 2 3 4 5 VCOM (V)
SUPPLY CURRENT vs. TEMPERATURE
MAX4731-33 toc07
LOGIC THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
MAX4731-33 toc08
TURN-ON/OFF TIME vs. SUPPLY VOLTAGE
MAX4731-33 toc09
4.0 3.5 SUPPLY CURRENT (nA) 3.0 2.5 2.0 1.5 1.0 0.5 0 -40
3.0 LOGIC THRESHOLD VOLTAGE (V) 2.5 2.0
V+ = +5V, +3V
VIN RISING OR FALLING
120 100 80 tON/OFF (ns) tON 60 40 20 0 tOFF
1.5 1.0 0.5 0
-20
0
20
40
60
80
2
4
6 V+ (V)
8
10
2
4
6 V+ (V)
8
10
TEMPERATURE (C)
6
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50, Dual SPST Analog Switches in UCSP MAX4731/MAX4732/MAX4733
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
TURN-ON/OFF TIME vs. TEMPERATURE
MAX4731-33 toc10
FREQUENCY RESPONSE
MAX4731-33 toc11
TOTAL HARMONIC DISTORTION vs. FREQUENCY
RL = 1k V+ = +3.0V 0.1 THD (%) RL = 1k V+ = +5.0V RL = 100k V+ = +3.0V 0.001 VCOM = 2VP-P BW = 30kHz
MAX4731-33 toc12
80 70 60 tON/OFF (ns) 50 40 30 20 10 0 -40 -20 0 20 tOFF, V+ = +3.0V tOFF, V+ = +5.0V 40 60 tON, V+ = +3.0V tON, V+ = +5.0V
1
0 -20 LOSS (dB) -40 OFF-ISOLATION -60 -80 -100 -120 CROSSTALK V+ = +3V 10k 100k 1M 10M 100M ON-LOSS
0.01
RL = 100k V+ = +5.0V 0.0001 1G 10 100 1k FREQUENCY (Hz) 10k 100k
80
TEMPERATURE (C)
FREQUENCY (Hz)
Pin Description
PIN MAX4731 UCSP A1 A2 A3 B1 B3 C1 C2 C3 -- -- -- MAX/ TDFN 1 2 4 7 3 8 6 5 -- -- EP (TDFN only) MAX4732 UCSP -- A2 A3 B1 B3 C1 C2 -- A1 C3 -- MAX/ TDFN -- 2 4 7 3 8 6 -- 1 5 EP (TDFN only) MAX4733 UCSP A1 A2 A3 B1 B3 C1 C2 -- -- C3 -- MAX/ TDFN 1 2 4 7 3 8 6 -- -- 5 EP (TDFN only) NO1 COM1 GND IN1 IN2 V+ COM2 NO2 NC1 NC2 EP Analog-Switch Normally Open Terminal Analog-Switch Common Terminal Ground. Connect to digital ground. Logic-Control Digital Input Logic-Control Digital Input Positive Supply Voltage Input Analog-Switch Common Terminal Analog-Switch Normally Open Terminal Analog-Switch Normally Closed Terminal Analog-Switch Normally Closed Terminal Exposed Pad. Connect to V+. NAME FUNCTION
Applications Information
Operating Considerations for High-Voltage Supply
The MAX4731/MAX4732/MAX4733 operate to +11V with some precautions. The absolute maximum rating for V+ is +12V (referenced to GND). When operating near this region, bypass V+ with a minimum 0.1F capacitor to ground as close to the IC as possible.
Logic Levels
The MAX4731/MAX4732/MAX4733 are TTL compatible when powered from a single +5V supply. When powered from other supply voltages, the logic inputs should be driven rail-to-rail. For example, with a +11V supply, IN1 and IN2 should be driven low to 0V and high to 11V. With a +3.3V supply, IN1 and IN2 should be driven low to 0V and high to 3.3V. Driving IN1 and IN2 railto-rail minimizes power consumption.
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7
50, Dual SPST Analog Switches in UCSP MAX4731/MAX4732/MAX4733
Analog Signal Levels
Analog signals that range over the entire supply voltage (GND to V+) pass with very little change in RON (see Typical Operating Characteristics). The bidirectional switches allow NO_, NC_, and COM_ connections to be used as either inputs or outputs.
UCSP Applications Information
For the latest application details on USCP construction, dimensions, tape carrier information, printed circuit board techniques, bump-pad layout, and recommended reflow temperature profile as well as the latest information on reliability testing results, go to the Maxim web site at www.maxim-ic.com/ucsp to find the Application Note: UCSP--A Wafer-Level Chip-Scale Package.
Power-Supply Sequencing and Overvoltage Protection
CAUTION: Do not exceed the absolute maximum ratings. Stresses beyond the listed ratings can cause permanent damage to the devices. Proper power-supply sequencing is recommended for all CMOS devices. Always apply V+ before applying analog signals, especially if the analog signal is not current limited. If this sequencing is not possible, and if the analog inputs are not current limited to < 20mA, add a small-signal diode, D1, as shown in Figure 1. If the analog signal can dip below GND, add D2. Adding protection diodes reduces the analog signal range to a diode drop (about 0.7V) below V+ (for D1), and to a diode drop above ground (for D2). Leakage is unaffected by adding the diodes. On-resistance increases slightly at low supply voltages. Maximum supply voltage (V+) must not exceed +11V. Adding protection diodes causes the logic thresholds to be shifted relative to the power-supply rails. The most significant shift occurs when using low supply voltages (+5V or less). With a +5V supply, TTL compatibility is not guaranteed when protection diodes are added. Driving IN1 and IN2 all the way to the supply rails (i.e., to a diode drop higher than the V+ pin, or to a diode drop lower than the GND pin) is always acceptable. Protection diodes D1 and D2 also protect against some overvoltage situations. Using the circuit in Figure 1, no damage results if the supply voltage is below the absolute maximum rating (+12V) and if a fault voltage up to the absolute maximum rating (V+ + 0.3V) is applied to an analog signal terminal.
Test Circuits/Timing Diagrams
V+ EXTERNAL BLOCKING DIODE D1
V+
MAX4731 MAX4732 MAX4733
*
NO_
*
COM_
*
GND
*
EXTERNAL BLOCKING DIODE GND
D2
*INTERNAL PROTECTION DIODES.
Figure 1. Overvoltage Protection Using External Blocking Diodes
8
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50, Dual SPST Analog Switches in UCSP MAX4731/MAX4732/MAX4733
Test Circuits/Timing Diagrams (continued)
MAX4731 MAX4732 MAX4733
VN_ V+ NO_ OR NC_ V+ COM_ RL 300 IN_ LOGIC INPUT GND SWITCH OUTPUT 0V tON LOGIC INPUT VOUT CL 35pF VOUT 0.9 x VOUT tOFF VIH 50% VIL
tr < 5ns tf < 5ns
0.9 x VOUT
CL INCLUDES FIXTURE AND STRAY CAPACITANCE. RL VOUT = VN_ ( R + R )
L ON
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 2. Switching Time
MAX4733
NO1 NC2 IN1 LOGIC INPUT IN2 GND
V+ V+ VOUT1 VOUT2 RL2 300 CL2 35pF CL1 35pF LOGIC INPUT
V+ 50% 0V
tr < 5ns tf < 5ns
VN_
COM1 COM2 RL1 300
SWITCH OUTPUT 1 (VOUT1) SWITCH OUTPUT 2 (VOUT2)
0.9 x V0UT1 0V
0.9 x VOUT2 0V tBBM tBBM
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 3. Break-Before-Make Interval (MAX4733 only)
V+
MAX4731 MAX4732 MAX4733
VOUT VOUT VOUT IN OFF ON OFF
V+ RGEN NC_ OR NO_ GND IN_ COM CL 1nF
V GEN
VIL TO VIH
IN
OFF
ON Q = (V OUT )(C L )
OFF
IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge Injection _______________________________________________________________________________________ 9
50, Dual SPST Analog Switches in UCSP MAX4731/MAX4732/MAX4733
Test Circuits/Timing Diagrams (continued)
10nF SIGNAL GENERATOR 0dBm V+ 10nF V+
V+ COM_
MAX4731 MAX4732 MAX4733
SIGNAL GENERATOR 0dBm
V+ COM1 IN1
MAX4731 MAX4732 MAX4733
NO1/NC1 IN2 0 OR 2.4V COM2 GND 50
IN_ ANALYZER RL NC_ OR NO_ GND 10nF
VIL OR VIH
0 OR 2.4V
ANALYZER RL
NO2/NC2
N.C.
10nF
VNOTE: DUAL SUPPLIES USED TO ACCOMODATE GROUND-REFERENCED INSTRUMENTS.
VNOTE: DUAL SUPPLIES USED TO ACCOMODATE GROUND-REFERENCED INSTRUMENTS.
Figure 5. Off-Isolation/On-Channel Bandwidth
10nF V+
Figure 6. Crosstalk
V+ COM_
MAX4731 MAX4732 MAX4733
IN_ CAPACITANCE METER f = 1MHz NC_ OR NO_ GND
Chip Information
VIL OR VIH
TRANSITOR COUNT: 68 PROCESS: CMOS
Figure 7. Channel Off/On-Capacitance
10
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50, Dual SPST Analog Switches in UCSP
Pin Configurations/Functional Diagrams/Truth Tables (continued)
TOP VIEW (BUMPS ON BOTTOM)
NO1
IN1 V+
MAX4731/MAX4732/MAX4733
MAX4733
COM1
MAX4733
A3 B3 GND IN2 NC2
GND 4 TDFN EP = EXPOSED PAD 5 NC2 EP NO1 COM1 IN2 1 2 3 8 7 6 V+ IN1 COM2
A1 B1 C1
A2
MAX4733 IN_ 0 1 NO1 OFF ON NC2 ON OFF
C2 COM2 UCSP
C3
SWITCHES SHOWN FOR LOGIC "0" INPUT
TOP VIEW MAX4731
NO1 1 COM1 2 IN2 GND 3 4 8 7 6 5 V+ IN1 COM2 NO2 NC1 1 COM1 2 IN2 3 GND 4
MAX4732
8 7 6 5 V+ IN1 COM2 NC2 NO1 1 COM1 2 IN2 3 GND 4
MAX4733
8 7 6 5 V+ IN1 COM2 NC2
MAX
MAX
MAX
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11
50, Dual SPST Analog Switches in UCSP MAX4731/MAX4732/MAX4733
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 3x3 UCSP
21-0093
K
1 1
12
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9LUCSP, 3x3.EPS
50, Dual SPST Analog Switches in UCSP
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
MAX4731/MAX4732/MAX4733
PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm
21-0137
H
1 2
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 0.20 MAX. 0.80 3.10 3.10 0.05 0.40
PACKAGE VARIATIONS PKG. CODE T633-1 T633-2 T833-1 T833-2 T833-3 T1033-1 T1033-2 T1433-1 T1433-2 N 6 6 8 8 8 10 10 14 14 D2 1.50-0.10 1.50-0.10 1.50-0.10 1.50-0.10 1.50-0.10 1.50-0.10 1.50-0.10 1.70-0.10 1.70-0.10 E2 2.30-0.10 2.30-0.10 2.30-0.10 2.30-0.10 2.30-0.10 2.30-0.10 2.30-0.10 2.30-0.10 2.30-0.10 e 0.95 BSC 0.95 BSC 0.65 BSC 0.65 BSC 0.65 BSC 0.50 BSC 0.50 BSC 0.40 BSC 0.40 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEA MO229 / WEEC MO229 / WEEC MO229 / WEEC MO229 / WEED-3 MO229 / WEED-3 ------b 0.40-0.05 0.40-0.05 0.30-0.05 0.30-0.05 0.30-0.05 0.25-0.05 0.25-0.05 0.20-0.05 0.20-0.05 [(N/2)-1] x e 1.90 REF 1.90 REF 1.95 REF 1.95 REF 1.95 REF 2.00 REF 2.00 REF 2.40 REF 2.40 REF
0.25 MIN. 0.20 REF.
PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm
-DRAWING NOT TO SCALE-
21-0137
H
2 2
______________________________________________________________________________________
13
50, Dual SPST Analog Switches in UCSP MAX4731/MAX4732/MAX4733
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
4X S
8
8
INCHES DIM A A1 A2 b MIN 0.002 0.030 MAX 0.043 0.006 0.037
MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95
fl0.50-0.1
E
H
0.6-0.1
c D e E H L
1
1
0.6-0.1
S
D
BOTTOM VIEW
0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6 0 0.0207 BSC
0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 4.78 5.03 0.41 0.66 0 6 0.5250 BSC
TOP VIEW
A2
A1
A
c e b L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0036
1 1
J
Revision History
Pages changed at Rev 2: 1, 2, 7, 8, 11, 14
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
8LUMAXD.EPS

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